Z8F6421PM020SC Datasheet, PDF (94/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
74
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 38) contains the master enable bit for all
interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS
7
6
5
4
3
2
1
0
FIELD ^IRQE
Reserved
RESET
0
R/W
R/W
R
ADDR
FCFH
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset.
0 = Interrupts are disabled
1 = Interrupts are enabled
Reserved
Must be 0.
PS019915-1005
Interrupt Controller