Z8F6421PM020SC Datasheet, PDF (68/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
48
STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP
Mode Recovery sequence. In the Watch-Dog Timer Control register, the WDT and STOP
bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon time-
out and the 64K Series devices are configured to respond to interrupts, the eZ8 CPU ser-
vices the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery
sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition HALT
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source.
On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin
value (from High to Low or from Low to High) initiates STOP Mode Recovery. The GPIO
STOP Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in dura-
tion. In the Watch-Dog Timer Control register, the STOP bit is set to 1.
Caution:
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled.
The Port Input Data registers record the Port transition only if the signal
stays on the Port pin through the end of the STOP Mode Recovery delay.
Thus, short pulses on the Port pin can initiate STOP Mode Recovery with-
out being written to the Port Input Data register or without initiating an in-
terrupt (if enabled for that pin).
PS019915-1005
Reset and STOP Mode Recovery