Z8F6421PM020SC Datasheet, PDF (55/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Z8 Encore!
35
ADC Data High Byte
ADCD_H (F72H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Data [9:2]
ADC Data Low Bits
ADCD_L (F73H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
ADC Data [1:0]
DMA0 Address High Nibble
DMA0H (FB2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start Address [11:8]
DMA0 End Address [11:8]
DMA0 Start/Current Address Low Byte
DMA0START (FB3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start Address [7:0]
DMA0 Control
DMA0CTL (FB0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Received Data register
contains valid data
101 = UART1 Received Data register
contains valid data
110 = I2C receiver contains valid data
111 = Reserved
Word Select
0 = DMA transfers 1 byte per request
1 = DMA transfers 2 bytes per request
DMA0 Interrupt Enable
0 = DMA0 does not generate interrupts
1 = DMA0 generates an interrupt when
End Address data is transferred
DMA0 Data Transfer Direction
0 = Register File to peripheral registers
1 = Peripheral registers to Register File
DMA0 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to run
DMA0 Enable
0 = DMA0 is disabled
1 = DMA0 is enabled
DMA0 I/O Address
DMA0IO (FB1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Peripheral Register Address
Low byte of on-chip peripheral control
registers on Register File page FH
DMA0 End Address Low Byte
DMA0END (FB4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 End Address [7:0]
DMA1 Control
DMA1CTL (FB8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
100 = UART0 Transmit Data register
is empty
101 = UART1 Transmit Data register
is empty
110 = I2C Transmit Data register
is empty
111 = Reserved
Word Select
0 = DMA transfers 1 byte per request
1 = DMA transfers 2 bytes per request
DMA1 Interrupt Enable
0 = DMA1 does not generate interrupts
1 = DMA1 generates an interrupt when
End Address data is transferred
DMA1 Data Transfer Direction
0 = Register File to peripheral registers
1 = Peripheral registers to Register File
DMA1 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to run
DMA1 Enable
0 = DMA1 is disabled
1 = DMA1 is enabled
PS019915-1005
Control Register Summary