Z8F6421PM020SC Datasheet, PDF (217/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
197
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
• Serial Break (a minimum of nine continuous bits Low)
• Framing Error (received Stop bit is Low)
• Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a Serial Break 4096 system clock cycles long back to the host, and resets the
Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by
the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter-
face, returning a Serial Break break back to the host only extends the length of the Serial
Break if the host releases the Serial Break early.
The host transmits a Serial Break on the DBG pin when first connecting to the 64K Series
devices or when recovering from an error. A Serial Break from the host resets the Auto-
Baud Generator/Detector but does not reset the OCD Control register. A Serial Break
leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset
until the end of the Serial Break when the DBG pin returns High. Because of the open-
drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD
is transmitting a character.
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are
enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If Breakpoints are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.
If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the inter-
rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine.
For interrupts to be serviced in the background, interrupts must also be enabled. Debug-
ging software should not automatically enable interrupts when using this feature, since
interrupts are typically disabled during critical sections of code where interrupts should
not occur (such as adjusting the stack pointer or modifying shared data).
Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop-
ing on a BRK instruction. When software wants to stop the CPU on the BRK instruction it
is looping on, software should not set the DBGMODE bit of the OCDCTL register. The
CPU may have vectored to and be in the middle of an interrupt service routine when this
bit gets set. Instead, software must clear the BRKLP bit. This action allows the CPU to
PS019915-1005
On-Chip Debugger