Z8F6421PM020SC Datasheet, PDF (251/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
231
UART Timing
Figure 56 and Table 119 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data register has
been loaded with data prior to CTS assertion.
CTS
(Input)
DE
(Output)
TXD
(Output)
T₁
T₂
Start Bit 0 Bit 1
T₃
Bit 7 Parity ^Stop
End of
Stop Bit(s)
Figure 56. UART Timing with CTS
Table 119. UART Timing with CTS
Delay (ns)
Parameter Abbreviation
T₁
CTS Fall to DE Assertion Delay
Minimum
Maximum
2 * XIN period 2 * XIN period
+ 1 Bit period
T₂
DE Assertion to TXD Falling Edge (Start) Delay 1 Bit period 1 Bit period +
1 * XIN period
T₃
End of Stop Bit(s) to DE Deassertion Delay
1 * XIN period 2 * XIN period
PS019915-1005
Electrical Characteristics