Z8F6421PM020SC Datasheet, PDF (41/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
21
Register File Address Map
Table 7 provides the address map for the Register File of the 64K Series products. Not all
devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports.
Consider registers for unimplemented peripherals as Reserved.
Table 7. 64K Series Register File Address Map
Address (Hex) Register Description
General Purpose RAM
000-EFF
General-Purpose Register File RAM
Timer 0
F00
F01
F02
F03
Timer 0 High Byte
Timer 0 Low Byte
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
F04
Timer 0 PWM High Byte
F05
Timer 0 PWM Low Byte
F06
Timer 0 Control 0
F07
Timer 0 Control 1
Timer 1
F08
F09
F0A
F0B
F0C
Timer 1 High Byte
Timer 1 Low Byte
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
F0D
Timer 1 PWM Low Byte
F0E
Timer 1 Control 0
F0F
Timer 1 Control 1
Timer 2
F10
F11
F12
F13
Timer 2 High Byte
Timer 2 Low Byte
Timer 2 Reload High Byte
Timer 2 Reload Low Byte
F14
Timer 2 PWM High Byte
F15
Timer 2 PWM Low Byte
F16
Timer 2 Control 0
F17
Timer 2 Control 1
XX=Undefined
Mnemonic Reset (Hex) Page #
—
XX
T0H
00
84
T0L
01
84
T0RH
FF
85
T0RL
FF
85
T0PWMH 00
87
T0PWML
00
87
T0CTL0
00
88
T0CTL1
00
88
T1H
00
84
T1L
01
84
T1RH
FF
85
T1RL
FF
85
T1PWMH 00
87
T1PWML
00
87
T1CTL0
00
88
T1CTL1
00
88
T2H
00
84
T2L
01
84
T2RH
FF
85
T2RL
FF
85
T2PWMH 00
87
T2PWML
00
87
T2CTL0
00
88
T2CTL1
00
88
PS019915-1005
Register File Address Map