Z8F6421PM020SC Datasheet, PDF (162/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
142
Transmit interrupts occur when the TDRE bit of the I²C Status register sets and the TXI
bit in the I²C Control register is set. Transmit interrupts occur under the following condi-
tions when the transmit data register is empty:
• The I²C Controller is enabled
• The first bit of the byte of an address is shifting out and the RD bit of the I²C Status
register is deasserted.
• The first bit of a 10-bit address shifts out.
• The first bit of write data shifts out.
Note: Writing to the I²C Data register always clears the TRDE bit to 0. When TDRE is asserted,
the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out until the Data register is written with the next value to send or the STOP or
START bits are set indicating the current byte is the last one to send.
The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled
(IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an inter-
rupt is generated when the baud rate generator counts down to 1. This allows the I²C baud
rate generator to be used by software as a general purpose timer when IEN = 0.
Software Control of I²C Transactions
Software can control I²C transactions by using the I²C Controller interrupt, by polling the
I²C Status register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I²C interrupt must be enabled in the Interrupt Controller. The TXI bit
in the I²C Control register must be set to enable transmit interrupts.
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I²C
Status register should be polled. The TDRE bit asserts regardless of the state of the TXI
bit.
Either or both transmit and receive data movement can be controlled by the DMA Control-
ler. The DMA Controller channel(s) must be initialized to select the I²C transmit and
receive requests. Transmit DMA requests require that the TXI bit in the I²C Control regis-
ter be set.
Caution:
A transmit (write) DMA operation hangs if the slave responds with a Not
Acknowledge before the last byte has been sent. After receiving the Not
Acknowledge, the I²C Controller sets the NCKI bit in the Status register
and pauses until either the STOP or START bits in the Control register are
set.
PS019915-1005
I2C Controller