Z8F6421PM020SC Datasheet, PDF (67/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
47
cycles, the devices progress through the System Reset sequence. While the RESET input
pin is asserted Low, the 64K Series devices continue to be held in the Reset state. If the
RESET pin is held Low beyond the System Reset time-out, the devices exit the Reset state
immediately following RESET pin deassertion. Following a System Reset initiated by the
external RESET pin, the EXT status bit in the Watch-Dog Timer Control (WDTCTL) reg-
ister is set to 1.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RST bit in
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The RST bit automatically clears during the system
reset. Following the system reset the POR bit in the WDT Control register is set.
STOP Mode Recovery
STOP mode is entered by the eZ8 executing a STOP instruction. Refer to the Section
Low-Power Modes on page 49 for detailed STOP mode information. During STOP Mode
Recovery, the devices are held in reset for 66 cycles of the Watch-Dog Timer oscillator
followed by 16 cycles of the system clock. STOP Mode Recovery only affects the contents
of the Watch-Dog Timer Control register. STOP Mode Recovery does not affect any other
values in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral
control registers, and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following STOP Mode Recovery, the STOP bit in the Watch-Dog Timer Con-
trol Register is set to 1. Table 10 lists the STOP Mode Recovery sources and resulting
actions. The text following provides more detailed information on each of the STOP Mode
Recovery sources.
Table 10. STOP Mode Recovery Sources and Resulting Action
Operating Mode
STOP mode
STOP Mode Recovery Source
Watch-Dog Timer time-out
when configured for Reset
Watch-Dog Timer time-out
when configured for interrupt
Data transition on any GPIO Port pin
enabled as a STOP Mode Recovery
source
Action
STOP Mode Recovery
STOP Mode Recovery followed by interrupt (if
interrupts are enabled)
STOP Mode Recovery
PS019915-1005
Reset and STOP Mode Recovery