Z8F6421PM020SC Datasheet, PDF (157/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
137
110 = 6 bits
111 = 7 bits.
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave.
SPI Diagnostic State Register
The SPI Diagnostic State register (Table 66) provides observability of internal state. This
is a read only register used for SPI diagnostics.
Table 66. SPI Diagnostic State Register (SPIDST)
BITS
7
6
5
4
3
2
1
0
FIELD ^{SCKEN TCKEN}
SPISTATE
RESET
R/W
ADDR
0
R
F64H
SCKEN - Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-
tem clock)
TCKEN - Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
SPISTATE - SPI State Machine
Defines the current state of the internal SPI State Machine.
PS019915-1005
Serial Peripheral Interface