Z8F6421PM020SC Datasheet, PDF (155/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
135
SPI Status Register
The SPI Status register (Table 64) indicates the current state of the SPI. All bits revert to
their reset state if the SPIEN bit in the SPICTL register = 0.
Table 64. SPI Status Register (SPISTAT)
BITS
7
6
5
4
FIELD ^IRQ
OVR
COL
ABT
RESET
0
3
2
Reserved
R/W
R/W*
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
F62H
1
TXST
R
0
SLAS
1
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
pleted.
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved—Must be 0.
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
PS019915-1005
Serial Peripheral Interface