Z8F6421PM020SC Datasheet, PDF (224/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
204
RST—Reset
Setting this bit to 1 resets the 64K Series devices. The devices go through a normal Power-
On Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is
automatically cleared to 0 when the reset finishes.
0 = No effect
1 = Reset the 64K Series device
OCD Status Register
The OCD Status register (Table 102) reports status information about the current state of
the debugger and the system.
Table 102. OCD Status Register (OCDSTAT)
BITS
7
6
5
4
3
2
1
0
FIELD ^IDLE
HALT
RPEN
Reserved
RESET
0
R/W
R
IDLE—CPU idling
This bit is set if the part is in DEBUG mode (DBGMODE is 1), or if a BRK instruction
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (1).
1 = The Read Protect Option Bit is enabled (0), disabling many OCD commands.
Reserved
These bits are always 0.
PS019915-1005
On-Chip Debugger