Z8F6421PM020SC Datasheet, PDF (114/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
94
1. Write 55H to the Watch-Dog Timer Control register (WDTCTL).
2. Write AAH to the Watch-Dog Timer Control register (WDTCTL).
3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU).
4. Write the Watch-Dog Timer Reload High Byte register (WDTH).
5. Write the Watch-Dog Timer Reload Low Byte register (WDTL).
All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order
just listed. There must be no other register writes between each of these operations. If a
register write occurs, the lock state machine resets and no further writes can occur, unless
the sequence is restarted. The value in the Watch-Dog Timer Reload registers is loaded
into the counter when the Watch-Dog Timer is first enabled and every time a WDT
instruction is executed.
Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register, detailed in Table 47, is a Read-Only
register that indicates the source of the most recent Reset event, indicates a STOP Mode
Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets
the upper four bits to 0.
Writing the 55H, AAH unlock sequence to the Watch-Dog Timer Control (WDTCTL) reg-
ister address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH,
and WDTL) to allow changes to the time-out period. These write operations to the
WDTCTL register address produce no effect on the bits in the WDTCTL register. The
locking mechanism prevents spurious writes to the Reload registers.
Table 47. Watch-Dog Timer Control Register (WDTCTL)
BITS
7
6
5
4
3
2
1
0
FIELD ^POR
STOP
WDT
EXT
Reserved
SM
RESET
See descriptions below
0
R/W
R
ADDR
FF0H
PS019915-1005
Watch-Dog Timer