Z8F6421PM020SC Datasheet, PDF (167/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
147
7. The I²C Controller loads the I²C Shift register with the contents of the I²C Data
register.
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I²C
Data register.
10. The I²C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I²C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL the I²C Controller sets the ACK bit in the I²C Status register.
Continue with step 12.
If the slave does not acknowledge the first address byte, the I²C Controller sets the
NCKI bit and clears the ACK bit in the I²C Status register. Software respons to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
12. The I²C Controller loads the I²C Shift register with the contents of the I²C Data
register (2nd byte of address).
13. The I²C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit interrupt is asserted.
14. Software responds by setting the STOP bit in the I2C Control register. The TXI bit can
be cleared at the same time.
15. Software polls the STOP bit of the I²C Control register. Hardware deasserts the STOP
bit when the transaction is completed (STOP condition has been sent).
16. Software checks the ACK bit of the I²C Status register. If the slave acknowledged, the
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt do not occur because the STOP bit was set.
Write Transaction with a 10-Bit Address
Figure 31 illustrates the data transfer format for a 10-bit addressed slave. Shaded regions
indicate data transferred from the I²C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I²C Controller.
S
Slave Address
1st 7 bits
W=0 A
Slave Address
2nd Byte
A Data A Data A/A P/S
Figure 31. 10-Bit Addressed Slave Data Transfer Format
PS019915-1005
I2C Controller