Z8F6421PM020SC Datasheet, PDF (163/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
143
In order for a receive (read) DMA transaction to send a Not Acknowledge
on the last byte, the receive DMA must be set up to receive n-1 bytes, then
software must set the NAK bit and receive the last (nth) byte directly.
Start and Stop Conditions
The master (I²C) drives all Start and Stop signals and initiates all transactions. To start a
transaction, the I²C Controller generates a START condition by pulling the SDA signal
Low while SCL is High. To complete a transaction, the I²C Controller generates a Stop
condition by creating a low-to-high transition of the SDA signal while the SCL signal is
high. The START and STOP bits in the I²C Control register control the sending of the
Start and Stop conditions. A master is also allowed to end one transaction and begin a new
one by issuing a Restart. This is accomplished by setting the START bit at the end of a
transaction, rather than the STOP bit. Note that the Start condition not sent until the
START bit is set and data has been written to the I²C Data register.
Master Write and Read Transactions
The following sections provide a recommended procedure for performing I²C write and
read transactions from the I²C Controller (master) to slave I²C devices. In general soft-
ware should rely on the TDRE, RDRF and NCKI bits of the status register (these bits gen-
erate interrupts) to initiate software actions. When using interrupts or DMA, the TXI bit is
set to start each transaction and cleared at the end of each transaction to eliminate a “trail-
ing” Transmit interrupt.
Caution should be used in using the ACK status bit within a transaction because it is diffi-
cult for software to tell when it is updated by hardware.
When writing data to a slave, the I²C pauses at the beginning of the Acknowledge cycle if
the data register has not been written with the next value to be sent (TDRE bit in the I²C
Status register = 1). In this scenario where software is not keeping up with the I²C bus
(TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is
delayed until the Data register is written with byte n + 1, and appears to be grouped with
the data clock cycles for byte n+1. If either the START or STOP bit is set, the I²C does not
pause prior to the Acknowledge cycle because no additional data is sent.
When a Not Acknowledge condition is received during a write (either during the address
or data phases), the I²C Controller generates the Not Acknowledge interrupt (NCKI = 1)
and pause until either the STOP or START bit is set. Unless the Not Acknowledge was
received on the last byte, the Data register will already have been written with the next
address or data byte to send. In this case the FLUSH bit of the Control register should be
set at the same time the STOP or START bit is set to remove the stale transmit data and
enable subsequent Transmit interrupts.
When reading data from the slave, the I²C pauses after the data Acknowledge cycle until
the receive interrupt is serviced and the RDRF bit of the status register is cleared by read-
PS019915-1005
I2C Controller