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Z8F6421PM020SC Datasheet, PDF (154/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series | |||
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Z8 Encore!® 64K Series
Product Specification
134
Table 63. SPI Control Register (SPICTL)
BITS
7
6
5
4
3
2
1
0
FIELD IRQE
STR
BIRQ PHASE CLKPOL WOR MMEN SPIEN
RESET
0
R/W
R/W
ADDR
F61H
IRQEâInterrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STRâStart an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the
IRQ bit in the SPI Status register clears this bit to 0.
BIRQâBRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PHASEâPhase Select
Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and
Polarity Control section for more information on operation of the PHASE bit.
CLKPOLâClock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WORâWire-OR (Open-Drain) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMENâSPI Master Mode Enable
0 = SPI configured in Slave mode.
1 = SPI configured in Master mode.
SPIENâSPI Enable
0 = SPI disabled.
1 = SPI enabled.
PS019915-1005
Serial Peripheral Interface
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