Z8F6421PM020SC Datasheet, PDF (172/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
152
16. The I²C Controller loads the I²C Shift register with the contents of the I²C Data
register (third address transfer).
17. The I²C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I²C slave sends an acknowledge by pulling the SDA signal Low during the next
high period of SCL
If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the
STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
19. The I²C Controller shifts in a byte of data from the I²C slave on the SDA signal. The
I²C Controller sends a Not Acknowledge to the I²C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
20. The I²C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
21. Software responds by reading the I²C Data register which clears the RDRF bit. If there
is only one more byte to receive, set the NAK bit of the I²C Control register.
22. If there are one or more bytes to transfer, return to step 19.
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I²C
Controller.
24. Software responds by setting the STOP bit of the I²C Control register.
25. A STOP condition is sent to the I²C slave and the STOP and NCKI bits are cleared.
I²C Control Register Definitions
I²C Data Register
The I²C Data register (Table 69) holds the data that is to be loaded into the I²C Shift regis-
ter during a write to a slave. This register also holds data that is loaded from the I²C Shift
PS019915-1005
I2C Controller