Z8F6421PM020SC Datasheet, PDF (248/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
228
SPI Master Mode Timing
Figure 53 and Table 116 provide timing information for SPI Master mode pins. Timing is
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK
T1
MOSI
(Output)
MISO
(Input)
Output Data
T2 T3
Input Data
Figure 53. SPI Master Mode Timing
Table 116. SPI Master Mode Timing
Parameter Abbreviation
SPI Master
T₁
SCK Rise to MOSI output Valid Delay
T₂
MISO input to SCK (receive edge) Setup Time
T₃
MISO input to SCK (receive edge) Hold Time
Delay (ns)
Min
Max
-5
+5
20
0
PS019915-1005
Electrical Characteristics