Z8F6421PM020SC Datasheet, PDF (185/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
165
101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
110 = DMA0 Control register: I²C Receiver Interrupt. DMA1 Control register: I²C Trans-
mitter Interrupt register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address register (Table 77) contains the low byte of the on-chip peripheral
address for data transfer. The full 12-bit Register File address is given by {FH,
DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the DMAx I/
O Address register must contain an even numbered address.
Table 77. DMAx I/O Address Register (DMAxIO)
BITS
7
6
5
4
3
2
1
0
FIELD
DMA_IO
RESET
X
R/W
R/W
ADDR
FB1H, FB9H
DMA_IO—DMA on-chip peripheral control register address
This byte sets the low byte of the on-chip peripheral control register address on Register
File Page FH (addresses F00H to FFFH).
DMAx Address High Nibble Register
The DMAx Address High register (Table 78) specifies the upper four bits of address for
the Start/Current and End Addresses of DMAx.
Table 78. DMAx Address High Nibble Register (DMAxH)
BITS
7
FIELD
RESET
R/W
6
5
DMA_END_H
4
3
2
1
0
DMA_START_H
X
R/W
ADDR
FB2H, FBAH
PS019915-1005
Direct Memory Access Controller