Z8F6421PM020SC Datasheet, PDF (115/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
95
Reset or STOP Mode Recovery Event
Power-On Reset
Reset using RESET pin assertion
Reset using Watch-Dog Timer time-out
Reset using the On-Chip Debugger (OCDCTL[1] set to 1)
Reset from STOP Mode using DBG Pin driven Low
STOP Mode Recovery using GPIO pin transition
STOP Mode Recovery using Watch-Dog Timer time-out
POR
1
0
0
1
1
0
0
STOP WDT
0
0
0
0
0
1
0
0
0
0
1
0
1
1
EXT
0
1
0
0
0
0
0
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-
out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—STOP Mode Recovery Indicator
If this bit is set to 1, a STOP Mode Recovery occurred. If the STOP and WDT bits are both
set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOP bit is 1
and the WDT bit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This
bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP
mode. Reading this register also resets this bit.
WDT—Watch-Dog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP
Mode Recovery from a change in an input pin also resets this bit. Reading this register
resets this bit.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
Reserved
These bits are reserved and must be 0.
SM—STOP Mode Configuration Indicator
0 = Watch-Dog Timer and its internal RC oscillator will continue to operate in STOP
Mode.
1 = Watch-Dog Timer and its internal RC oscillator will be disabled in STOP Mode.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-
isters (Tables 48 through 50) form the 24-bit reload value that is loaded into the Watch-
Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],
WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the desired Reload Value. Read-
ing from these registers returns the current Watch-Dog Timer count value.
PS019915-1005
Watch-Dog Timer