Z8F6421PM020SC Datasheet, PDF (149/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
129
Transfer Format PHASE Equals Zero
Figure 25 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to
0. The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set
to one. The diagram may be interpreted as either a Master or Slave timing diagram
because the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are
directly connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MISO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Input Sample Time
SS
Figure 25. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One
Figure 26 illustrates the timing diagram for an SPI transfer in which PHASE is one. Two
waveforms are depicted for SCK, one for CLKPOL reset to 0 and another for CLKPOL set
to 1.
PS019915-1005
Serial Peripheral Interface