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Z8F6421PM020SC Datasheet, PDF (90/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series | |||
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Z8 Encore!® 64K Series
Product Specification
70
T2ENHâTimer 2 Interrupt Request Enable High Bit
T1ENHâTimer 1 Interrupt Request Enable High Bit
T0ENHâTimer 0 Interrupt Request Enable High Bit
U0RENHâUART 0 Receive Interrupt Request Enable High Bit
U0TENHâUART 0 Transmit Interrupt Request Enable High Bit
I2CENHâI2C Interrupt Request Enable High Bit
SPIENHâSPI Interrupt Request Enable High Bit
ADCENHâADC Interrupt Request Enable High Bit
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
RESET
R/W
ADDR
7
T2ENL
6
T1ENL
5
T0ENL
4
3
U0RENL U0TENL
0
R/W
FC2H
2
I2CENL
1
0
SPIENL ADCENL
T2ENLâTimer 2 Interrupt Request Enable Low Bit
T1ENLâTimer 1 Interrupt Request Enable Low Bit
T0ENLâTimer 0 Interrupt Request Enable Low Bit
U0RENLâUART 0 Receive Interrupt Request Enable Low Bit
U0TENLâUART 0 Transmit Interrupt Request Enable Low Bit
I2CENLâI2C Interrupt Request Enable Low Bit
SPIENLâSPI Interrupt Request Enable Low Bit
ADCENLâADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (Tables 31 and 32) form a priority encoded
enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting
bits in each register. Table 30 describes the priority control for IRQ1.
Table 30. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
0
0
Disabled
Disabled
0
1
Level 1
Low
1
0
Level 2
Nominal
1
1
Level 3
High
where x indicates the register bits from 0 through 7.
PS019915-1005
Interrupt Controller
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