Z8F6421PM020SC Datasheet, PDF (112/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
92
Table 46. Watch-Dog Timer Approximate Time-Out Delays
WDT Reload Value
(Hex)
000004
FFFFFF
WDT Reload Value
(Decimal)
4
16,777,215
Approximate Time-Out Delay
(with 10kHz typical WDT oscillator frequency)
Typical
400μs
1677.5s
Description
Minimum time-out delay
Maximum time-out delay
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 000000H unless a
WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes
the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog
Timer Reload registers. Counting resumes following the reload operation.
When the 64K Series devices are operating in Debug Mode (through the On-Chip Debug-
ger), the Watch-Dog Timer is continuously refreshed to prevent spurious Watch-Dog
Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the
Watch-Dog Timer generates either an interrupt or a Reset. The WDT_RES Option Bit
determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chap-
ter for information regarding programming of the WDT_RES Option Bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watch-Dog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watch-Dog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watch-Dog Timer counter
rolls over to its maximum value of FFFFFH and continues counting. The Watch-Dog
Timer counter is not automatically returned to its Reload Value.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the 64K Series devices
are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery
and generates an interrupt request. Both the WDT status bit and the STOP bit in the Watch-
Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to
PS019915-1005
Watch-Dog Timer