Z8F6421PM020SC Datasheet, PDF (126/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
106
Start bit is transmitted. This timing allows a setup time to enable the transceiver. The
Driver Enable signal deasserts one system clock period after the last Stop bit is transmit-
ted. This one system clock delay allows both time for data to clear the transceiver before
disabling it, as well as the ability to determine if another character follows the current
character. In the event of back to back characters (new data must be written to the Trans-
mit Data Register before the previous character is completely transmitted) the DE signal is
not deasserted between characters. The DEPOL bit in the UART Control Register 1 sets the
polarity of the Driver Enable signal.
1
DE
0
Idle State
of Line
lsb
1
Data Field
Stop Bit
msb
Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Parity
0
1
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
⎛
⎝
B-----a--u---d-----R---1-a--t--e----(--H-----z---)^⎠⎞
≤
DE
to
Start
Bit
Setup
Time
(s)
≤
⎛
⎝
B-----a--u---d-----R---2-a--t--e----(--H-----z---)^⎠⎞
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first bit
of data out. At this point, the Transmit Data register may be written with the next character
to send. This provides 7 bit periods of latency to load the Transmit Data register before the
Transmit shift register completes shifting the current character. Writing to the UART
Transmit Data register clears the TDRE bit to 0.
PS019915-1005
UART