Z8F6421PM020SC Datasheet, PDF (109/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
89
ONE-SHOT mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
CONTINUOUS mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
PWM mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
CAPTURE mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
GATED mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
CAPTURE/COMPARE mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current
count is captured on subsequent falling edges of the Timer Input signal.
PS019915-1005
Timers