Z8F6421PM020SC Datasheet, PDF (84/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
64
Architecture
Figure 11 illustrates a block diagram of the interrupt controller.
Port Interrupts
Internal Interrupts
High
Priority
Medium
Priority
Vector
Priority
Mux
IRQ Request
Low
Priority
Figure 11. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
• Executing an EI (Enable Interrupt) instruction
• Executing an IRET (Return from Interrupt) instruction
• Writing a 1 to the IRQE bit in the Interrupt Control register
Interrupts are globally disabled by any of the following actions:
• Execution of a DI (Disable Interrupt) instruction
• eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller
• Writing a 0 to the IRQE bit in the Interrupt Control register
• Reset
PS019915-1005
Interrupt Controller