Z8F6421PM020SC Datasheet, PDF (175/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
155
I²C Control Register
The I²C Control register (Table 71) enables the I²C operation.
Table 71. I²C Control Register (I2CCTL)
BITS
7
FIELD ^IEN
RESET
R/W
R/W
ADDR
6
START
5
STOP
R/W1
R/W1
4
3
BIRQ
TXI
0
R/W
R/W
F52H
2
NAK
1
FLUSH
0
FILTEN
R/W1
W1
R/W
IEN—I²C Enable
1 = The I²C transmitter and receiver are enabled.
0 = The I²C transmitter and receiver are disabled.
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I²C Controller after it
sends the START condition or if the IEN bit is deasserted. If this bit is 1, it cannot be
cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if there
is data in the I²C Data or I²C Shift register. If there is no data in one of these registers, the
I²C Controller waits until the Data register is written. If this bit is set while the I²C Con-
troller is shifting out data, it generates a START condition after the byte shifts and the
acknowledge phase completes. If the STOP bit is also set, it also waits until the STOP con-
dition is sent before the sending the START condition.
STOP—Send Stop Condition
This bit causes the I²C Controller to issue a Stop condition after the byte in the I²C Shift
register has completed transmission or after a byte has been received in a receive opera-
tion. Once set, this bit is reset by the I²C Controller after a Stop condition has been sent or
by deasserting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the regis-
ter.
BIRQ—Baud Rate Generator Interrupt Request
This bit allows the I²C Controller to be used as an additional timer when the I2C Control-
ler is disabled. This bit is ignored when the I²C Controller is enabled.
1 = An interrupt occurs every time the baud rate generator counts down to one.
0 = No baud rate generator interrupt occurs.
TXI—Enable TDRE interrupts
This bit enables the transmit interrupt when the I²C Data register is empty (TDRE = 1).
1 = Transmit interrupt (and DMA transmit request) is enabled.
0 = Transmit interrupt (and DMA transmit request) is disabled.
PS019915-1005
I2C Controller