Z8F6421PM020SC Datasheet, PDF (176/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
156
NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from
the I²C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN
bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit to 1 clears the I²C Data register and sets the TDRE bit to 1. This bit allows
flushing of the I²C Data register when a Not Acknowledge interrupt is received after the
data has been sent to the I²C Data register. Reading this bit always returns 0.
FILTEN—I²C Signal Filter Enable
This bit enables low-pass digital filters on the SDA and SCL input signals. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
1 = low-pass filters are enabled.
0 = low-pass filters are disabled.
I²C Baud Rate High and Low Byte Registers
The I²C Baud Rate High and Low Byte registers (Tables 72 and 73) combine to form a 16-
bit reload value, BRG[15:0], for the I²C Baud Rate Generator.
When the I²C is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the I²C by clearing the IEN bit in the I²C Control register to 0.
2. Load the desired 16-bit count value into the I²C Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the I²C Control register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ]
PS019915-1005
I2C Controller