Z8F6421PM020SC Datasheet, PDF (173/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
153
register during a read from a slave. The I²C Shift Register is not accessible in the Register
File address space, but is used only to buffer incoming and outgoing data.
Table 69. I²C Data Register (I2CDATA)
BITS
7
6
5
4
3
2
1
0
FIELD
DATA
RESET
0
R/W
ADDR
R/W
F50H
I²C Status Register
The Read-only I²C Status register (Table 70) indicates the status of the I²C Controller.
Table 70. I²C Status Register (I2CSTAT)
BITS
FIELD
RESET
R/W
ADDR
7
TDRE
1
6
RDRF
5
ACK
4
3
10B
RD
0
R
F51H
2
1
0
TAS
DSS
NCKI
TDRE—Transmit Data Register Empty
When the I²C Controller is enabled, this bit is 1 when the I²C Data register is empty.
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I²C
Controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I²C Controller is enabled and the I²C Controller has received a
byte of data. When asserted, this bit causes the I²C Controller to generate an interrupt.
This bit is cleared by reading the I²C Data register (unless the read is performed using exe-
cution of the On-Chip Debugger’s Read Register command).
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
PS019915-1005
I2C Controller