Z8F6421PM020SC Datasheet, PDF (153/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
133
SPI Control Register Definitions
SPI Data Register
The SPI Data register (Table 62) stores both the outgoing (transmit) data and the incoming
(receive) data. Reads from the SPI Data register always return the current contents of the
8-bit shift register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error flag, OVR, is set in the SPI Status register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
register), the transmit character must be left justified in the SPI Data register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be writ-
ten to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
Table 62. SPI Data Register (SPIDATA)
BITS
7
6
5
4
3
2
1
0
FIELD
DATA
RESET
X
R/W
R/W
ADDR
F60H
DATA—Data
Transmit and/or receive data.
SPI Control Register
The SPI Control register (Table 63) configures the SPI for transmit and receive operations.
PS019915-1005
Serial Peripheral Interface