Z8F6421PM020SC Datasheet, PDF (160/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
140
Architecture
Figure 27 illustrates the architecture of the I²C Controller.
SDA
SCL
Baud Rate Generator
I²CBRH
I²CBRL
ISHIFT
Shift
Load
I²CDATA
Receive
Tx/Rx State Machine
I²CCTL
I²C Interrupt
Figure 27. I²C Controller Block Diagram
Register Bus
I²CSTAT
Operation
The I²C Controller operates in MASTER mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I²C supports the following operations:
• Master transmits to a 7-bit slave
• Master transmits to a 10-bit slave
PS019915-1005
I2C Controller