Z8F6421PM020SC Datasheet, PDF (93/299 Pages) Zilog, Inc. – High Performance 8-Bit Microcontrollers Z8 Encore-R 64K Series

Z8 Encore!^® 64K Series
Product Specification
73
Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
Table 36. Interrupt Edge Select Register (IRQES)
BITS
7
6
5
4
3
2
1
0
FIELD ^IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
RESET
0
R/W
R/W
ADDR
FCDH
IESx—Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of
the edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
where x indicates the specific GPIO Port pin number (0 through 7),
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 37) determines the port pin that generates the
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as inter-
rupts. The Interrupt Edge Select register controls the active interrupt edge.
Table 37. Interrupt Port Select Register (IRQPS)
BITS
7
6
5
4
3
FIELD ^{PAD7S PAD6S PAD5S PAD4S PAD3S}
RESET
R/W
ADDR
0
R/W
FCEH
2
PAD2S
1
PAD1S
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7)
0
PAD0S
PS019915-1005
Interrupt Controller