CP3BT23 Datasheet, PDF (70/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

14.0 Input/Output Ports
Each device has up to 50 software-configurable I/O pins, or- Different pins within the same port can be individually con-
ganized into 8-bit ports (not all bits are used in some ports). figured to operate in different modes.
The ports are named Port B, Port C, Port E, Port F, Port G, _{Figure 13 is a diagram showing the I/O port pin logic. The}
Port H, and Port J.
register bits, multiplexers, and buffers allow the port pin to
In addition to their general-purpose I/O capability, the I/O be configured into the various operating modes. The output
pins of Ports E, F, G, H, and J have alternate functions for buffer is a TRI-STATE buffer with weak pull-up capability.
use with on-chip peripheral modules such as the UART or The weak pull-up, if used, prevents the port pin from going
the Multi-Input Wake-Up unit. The alternate functions of all to an undefined state when it operates as an input.
I/O pins are shown in Table 86.
To reduce power consumption, input buffers configured for
Ports B and C are used as the 16-bit data bus when an ex- general-purpose I/O are only enabled when they are read.
ternal bus is enabled (144-pin devices only). This alternate When configured for an alternate function, the input buffers
function is selected by enabling the DEV or ERE operating are enabled continuously. To minimize power consumption,
environments, not by programming the port registers.
input signals to enabled buffers must be held within 0.2 volts
The I/O pin characteristics are fully programmable. Each pin ^{of the VCC or GND voltage.}
can be configured to operate as a TRI-STATE output, push- The electrical characteristics and drive capabilities of the in-
pull output, weak pull-up input, or high-impedance input. put and output buffers are described in Section 29.0.
PxALTS Register
te _{PxALT Register}
le ^{PxWKPU Register}
Alt. A Device Direction
Alt. B Device Direction
PxDIR Register
o _{Alt. A Device Data Outout}
Alt. B Device Data Outout
s _{PxDOUT Register}
Alt. A Data Input
b_{PxDIN Register}
Alt. B Data Input
O^{Data In Read Strobe}
DQ
DQ
DQ
DQ
DQ
VCC
Weak Pull-Up Enable
Output Enable
Pin
Data Out
Data In
1
Analog Input
DS190
Figure 13. I/O Port Pin Logic
14.1 PORT REGISTERS
Each port has an associated set of memory-mapped regis-
ters used for controlling the port and for holding the port da-
ta:
! PxALT: Port alternate function register
! PxALTS: Port alternate function select register
! PxDIR: Port direction register
! PxDIN: Port data input register
! PxDOUT: Port data output register
! PxWPU: Port weak pull-up register
! PxHDRV: Port high drive strength register
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