CP3BT23 Datasheet, PDF (46/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

9.6.6 Block Length Register (BLTRn)
DIR
The Transfer Direction bit specifies the direc-
The Block Length register is a 16-bit, read/write register. It
holds the number of DMA transfers to be performed for the
next block. Writing this register automatically sets the DM-
ASTAT.VLD bit.
tion of the transfer relative to Device A.
0 – Device A (pointed to by the ADCAn regis-
ter) is the source. In Fly-By mode a read
transaction is initialized.
1 – Device A (pointed to by the ADCAn regis-
ter) is the destination. In Fly-By mode a
15
0
write transaction is initialized.
Block Length
OT
The Operation Type bit specifies the operation
mode of the DMA controller.
0 – Single-buffer mode or double-buffer mode
Note: 0000h is interpreted as 2¹⁶-1 transfer cycles.
9.6.7 DMA Control Register (DMACNTLn)
BPC
enabled.
1 – Auto-Initialize mode enabled.
The Bus Policy Control bit specifies the bus
The DMA Control register n is a word-wide, read/write reg-
policy applied by the DMA controller. The op-
ister that controls the operation of DMA channel n. This reg-
ister is cleared at reset. Reserved bits must be written with
0.
7
6
5
4
3
21
0
BPC OT DIR IND TCS EOVR ETC CHEN
te ¹⁵
Res.
14 13
INCB
12
ADB
11 10
INCA
9
8
ADA SWRQ
SWRQ
CHEN
ole _ETC
s _EOVR
Ob ^TCS
The Channel Enable bit must be set to enable
any DMA operation on this channel. Writing a
1 to this bit starts a new DMA transfer even if
it is currently a 1. If all DMACNTLn.CHEN bits
are clear, the DMA clock is disabled to reduce
power.
0 – Channel disabled.
1 – Channel enabled.
If the Enable Interrupt on Terminal Count bit is
set, it enables an interrupt when the DMAS-
TAT.TC bit is set.
0 – Interrupt disabled.
1 – Interrupt enabled.
If the Enable Interrupt on OVR bit is set, it en-
ables an interrupt when the DMASTAT.OVR
bit is set.
0 – Interrupt disabled.
1 – Interrupt enabled.
The Transfer Cycle Size bit specifies the num-
ber of bytes transferred in each DMA transfer
cycle. In direct (fly-by) mode, undefined re-
ADA
INCA
ADB
eration mode can be either intermittent (cycle
stealing) or continuous (burst).
0 – Intermittent operation. The DMAC chan-
nel relinquishes the bus after each trans-
action, even if the request is still asserted.
1 – Continuous operation. The DMAC chan-
nel n uses the bus continuously as long
as the request is asserted. This mode can
only be used for software DMA requests.
For hardware DMA requests, the BPC bit
must be clear.
The Software DMA Request bit is written with
a 1 to initiate a software DMA request. Writing
a 0 to this bit deactivates the software DMA
request. The SWRQ bit must only be written
when the DMRQ signal for this channel is in-
active (DMASTAT.CHAC = 0).
0 – Software DMA request is inactive.
1 – Software DMA request is active.
If the Device A Address Control bit is set, it en-
ables updating the Device A address.
0 – ADCAn address unchanged.
1 – ADCAn address incremented or decre-
mented, according to INCA field of
DMACNTLn register.
The Increment/Decrement ADCAn field spec-
ifies the step size for the Device A address in-
crement/decrement.
00 – Increment ADCAn register by 1.
01 – Increment ADCAn register by 2.
10 – Decrement ADCAn register by 1.
11 – Decrement ADCAn register by 2.
If the Device B Address Control bit is set, it en-
ables updating the Device B Address.
sults occur if the TCS bit is not equal to the ad-
0 – ADCBn address unchanged.
dressed memory bus width.
1 – ADCBn address incremented or decre-
0 – Byte transfers (8 bits per cycle).
mented, according to INCB field of
1 – Word transfers (16 bits per cycle).
DMACNTLn register.
IND
The Direct/Indirect Transfer bit specifies the ^INCB
The Increment/Decrement ADCBn field spec-
transfer type.
ifies the step size for the Device B address in-
0 – Direct transfer (flyby).
crement/decrement.
1 – Indirect transfer (memory-to-memory).
00 – Increment ADCBn register by 1.
01 – Increment ADCBn register by 2.
10 – Decrement ADCBn register by 1.
11 – Decrement ADCBn register by 2.
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