CP3BT23 Datasheet, PDF (228/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

29.5 OUTPUT SIGNAL LEVELS
All output signals are powered by the digital supply (VCC).
Table 76 summarizes the states of the output signals during
the reset state (when VCC power exists in the reset state)
and during the Power Save mode.
The RESET and NMI input pins are active during the Power
Save mode. In order to guarantee that the Power Save cur-
rent not exceed 1 mA, these inputs must be driven to a volt-
age lower than 0.5V or higher than VCC - 0.5V. An input
voltage between 0.5V and (VCC - 0.5V) may result in power
consumption exceeding 1 mA.
Table 76 Output Pins During Reset and Power-Save
Signals on a Pin
Reset State
(with Vcc)
Power Save Mode
Comments
PB7:0
PC7:0
TRI-STATE
TRI-STATE
Previous state
Previous state
I/O ports will maintain their values when
entering power-save mode
PE5:0
TRI-STATE
Previous state
PF7:0
PG7:0
PH7:0
PJ7:0
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Previous state
Previous state
Previous state
Previous state
te ^{29.6 CLOCK AND RESET TIMING}
(Guaranteed by design. All timing except memory interface characterized not tested for production.)
Table 77 Clock and Reset Signals
Symbol Figure
Description
Reference
Min (ns)
le ^{Clock Input Signals}
t_X1p 108 X1 period
Rising Edge (RE) on X1 to
next RE on X1
83.33
t_X1h 108 X1 high time, external clock
At 2V level (Both Edges) (0.5 Tclk) - 5
o ^{tX1l 108 X1 low time, external clock}
t_X2p 108 X2 period^a
At 0.8V level (Both Edges) (0.5 Tclk) - 5
RE on X2 to next RE on X2 10,000
t_X2h 108 X2 high time, external clock
At 2V level (both edges) (0.5 Tclk) - 500
s ^tX2l ^{108 X2 low time, external clock}
At 0.8V level (both edges) (0.5 Tclk) - 500
t_IH 109 Input hold time (NMI, RXD1, RXD2) After RE on CLK
0
Reset and NMI Input Signals
b _{tIW 109 NMI Pulse Width}
t_RST 110 RESET Pulse Width
O ^tR
110 Vcc Rise Time
NMI Falling Edge (FE) to
RE
20
RESET FE to RE
100
0.1 Vcc to 0.9 Vcc
Max (ns)
83.33
a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be
used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed
this given limit.
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