CP3BT23 Datasheet, PDF (132/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

19.5.6 Network Mode
DMA Operation
In network mode, each frame sync signal marks the begin- When a complete data word has been received through the
ning of new frame. Each frame can consist of up to four SRD pin in a slot n, the new data word is transferred to the
slots. The audio interface operates in a similar way to nor- corresponding receive DMA register n (ARDRn). A DMA re-
mal mode, however, in network mode the transmitter and re- quest is asserted when the ARDRn register is full. If a new
ceiver can be assigned to specific slots within each frame as slot n data word is received while the ARDRn register is still
described below.
full, the ARDRn register will be overwritten with the new da-
19.5.7 Transmit
The transmitter only shifts out data during the assigned slot.
During all other slots the STD output is in TRI-STATE mode.
DMA Operation
ta.
FIFO Operation
When a complete word has been received, it is transferred
to the receive FIFO at the current location of the Receive
FIFO Write Pointer (RWP). After that, the RWP is automati-
When a complete data word has been transmitted through _{cally incremented by 1. Therefore, data received in the next}
the STD pin, a new data word is reloaded from the corre- _{slot is copied to the next higher FIFO location.}
sponding transmit DMA register n (ATDRn). A DMA request
is asserted when ATDRn is empty. If a new data word must
be transmitted in a slot n while ATDRn is still empty, the pre-
vious slot n data will be retransmitted.
FIFO Operation
When a complete data word has been transmitted through
the STD pin, a new data word is reloaded from the transmit
te ^{FIFO from the current location of the Transmit FIFO Read}
Pointer (TRP). After that, the TRP is automatically incre-
mented by 1. Therefore, the audio data to be transmitted in
the next slot of the frame is read from the next FIFO loca-
tion.
A write to the Audio Transmit FIFO Register (ATFR) results
le ^{in a write to the transmit FIFO at the current location of the}
Transmit FIFO Write Pointer (TWP). After every write oper-
ation to the transmit FIFO, the TWP is automatically incre-
mented by 1.
When the TRP is equal to the TWP and the last access to
o ^{the FIFO was a read operation (transfer to the ATSR), the}
transmit FIFO is empty. When an additional read operation
from the FIFO to the ATSR is performed (while the FIFO is
already empty), a transmit FIFO underrun occurs. In this
s ^{case, the read pointer (TRP) will be decremented by 1 (in-}
cremented by 15) and the previous data word will be trans-
mitted again. A transmit FIFO underrun is indicated by the
TXU bit in the Audio Interface Transmit Status and Control
Register (ATSCR). No transmit interrupt will be generated
b _{(even if enabled).}
If the current TRP is equal to the TWP and the last access
to the FIFO was a write operation (to the ATFR), the FIFO is
full. If an additional write to the ATFR is performed, a trans-
O ^{mit FIFO overrun occurs. This error condition is not prevent-}
A read from the Audio Receive FIFO Register (ARFR) re-
sults in a read from the receive FIFO at the current location
of the Receive FIFO Read Pointer (RRP). After every read
operation from the receive FIFO, the RRP is automatically
incremented by 1.
When the RRP is equal to the RWP and the last access to
the FIFO was a transfer to the ARFR, the receive FIFO is
full. When a new complete data word has been shifted into
the ARSR while the receive FIFO was already full, the shift
register overruns. In this case, the new data in the ARSR will
not be transferred to the FIFO and the RWP will not be in-
cremented. A receive FIFO overrun is indicated by the RXO
bit in the Audio Interface Receive Status and Control Regis-
ter (ARSCR). No receive interrupt will be generated (even if
enabled).
When the current RWP is equal to the TWP and the last ac-
cess to the receive FIFO was a read from ARFR, a receive
FIFO underrun has occurred. This error condition is not pre-
vented by hardware. Software must ensure that no receive
underrun occurs.
The receive frame synchronization pulse on the SRFS pin
(or SFS in synchronous mode) and the receive shift clock on
the SRCLK (or SCK in synchronous mode) may be gener-
ated internally, or they can be supplied by an external
source.
19.6 COMMUNICATION OPTIONS
19.6.1 Data Word Length
The word length of the audio data can be selected to be ei-
ther 8 or 16 bits. In 16-bit mode, all 16 bits of the transmit
and receive shift registers (ATSR and ARSR) are used. In 8-
bit mode, only the lower 8 bits of the transmit and receive
ed by hardware. Software must ensure that no transmit _{shift registers (ATSR and ARSR) are used.}
overrun occurs.
19.6.2 Frame Sync Signal
The transmit frame synchronization pulse on the SFS pin
and the transmit shift clock on the SCK pin may be generat- ^{The audio interface can be configured to use either long or}
ed internally, or they can be supplied by an external source. ^{short frame sync signals to mark the beginning of a new}
data frame. If the corresponding Frame Sync Select (FSS)
19.5.8 Receive
bit in the Audio Control and Status register is clear, the re-
The receive shift register (ARSR) receives data words of all ^{ceive and/or transmit path generates or recognizes short}
slots in the frame, regardless of the slot assignment of the ^{frame sync pulses with a length of one bit shift clock period.}
interface. However, only those ARSR contents are trans- ^{When these short frame sync pulses are used, the transfer}
ferred to the receive FIFO or DMA receive register which ^{of the first data bit or the first slot begins at the first positive}
were received during the assigned time slots. A receive in- ^{edge of the shift clock after the negative edge on the frame}
terrupt or DMA request is initiated when this occurs.
sync pulse.
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