CP3BT23 Datasheet, PDF (161/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

22.2 MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the MWDAT register, eight or
sixteen MSK clocks, depending on the mode selected, are
generated to shift the 8 or 16 bits of data, and then MSK
goes idle again. The MSK idle state can be either high or
low, depending on the SCIDL bit.
MSK
Shift
Out
End of Transfer
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
Data In
MSK
Data Out
Data In
MSK
Data Out
Data In
MSK
Sample
Point
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
Figure 83. Normal Mode (SCIDL = 0)
Shift
Out
te MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
le _{Figure 84. Normal Mode (SCIDL = 1)}
o Shift
Out
MSB
s _Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Ob^{Figure 85. Alternate Mode (SCIDL = 0)}
DS069
End of Transfer
Bit 0
(LSB)
Bit 0
(LSB)
DS070
End of Transfer
Bit 0
(LSB)
Bit 0
(LSB)
DS071
End of Transfer
Shift
Out
Data Out
Data In
MSB
Sample
Point
MSB
MSB - 1
MSB - 1
MSB - 2
MSB - 2
Bit 1
Bit 1
Figure 86. Alternate Mode (SCIDL = 1)
Bit 0
(LSB)
Bit 0
(LSB)
DS072
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