CP3BT23 Datasheet, PDF (194/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

26.2 VTU REGISTERS
26.2.1 Mode Control Register (MODE)
The VTU contains a total of 19 user accessible registers, as
listed in Table 74. All registers are word-wide and are initial-
ized to a known value upon reset. All software accesses to
the VTU registers must be word accesses.
The MODE register is a word-wide read/write register which
controls the mode selection of all four timer subsystems.
The register is clear after reset.
Table 74 VTU Registers
76
5
4
32
1
0
Name
Address
Description
TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN
MODE
IO1CTL
IO2CTL
FF FF80h
FF FF82h
FF FF84h
Mode Control Register
I/O Control Register 1
I/O Control Register 2
15 14 13
12 11 10 9
8
TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN
INTCTL
INTPND
CLK1PS
CLK2PS
COUNT1
PERCAP1
DTYCAP1
COUNT2
PERCAP2
DTYCAP2
COUNT3
PERCAP3
DTYCAP3
COUNT4
PERCAP4
DTYCAP4
FF FF86h
FF FF88h
FF FF8Ah
te ^{FF FF98h}
FF FF8Ch
FF FF8Eh
le ^{FF FF90h}
FF FF92h
FF FF94h
o _{FF FF96h}
s _{FF FF9Ah}
FF FF9Ch
b_{FF FF9Eh}
FF FFA0h
O^{FF FFA2h}
Interrupt Control
Register
Interrupt Pending
Register
Clock Prescaler
Register 1
Clock Prescaler
Register 2
Counter 1 Register
Period/Capture 1
Register
Duty Cycle/Capture 1
Register
Counter 2 Register
Period/Capture 2
Register
Duty Cycle/Capture 2
Register
Counter 3 Register
Period/Capture 3
Register
Duty Cycle/Capture 3
Register
Counter 4 Register
Period/Capture 4
Register
TxRUN
TMODx
The Timer Run bit controls whether the corre-
sponding timer is stopped or running. If set,
the associated counter and clock prescaler is
started depending on the mode of operation.
Once set, the clock to the clock prescaler and
the counter are enabled and the counter will
increment each time the clock prescaler
counter value matches the value defined in
the associated clock prescaler field (CxPR-
SC).
0 – Timer stopped.
1 – Timer running.
The Timer System Operating Mode field en-
ables or disables the Timer Subsystem and
defines its operating mode.
00 – Low-Power Mode. All clocks to the
counter subsystem are stopped. The
counter is stopped regardless of the val-
ue of the TxRUN bits. Read operations
to the Timer Subsystem will return the
last value; software must not perform
any write operations to the Timer Sub-
system while it is disabled since those
will be ignored.
01 – Dual 8-bit PWM mode. Each 8-bit
counter may individually be started or
stopped via its associated TxRUN bit.
The TIOx pins will function as PWM out-
puts.
10 – 16-bit PWM mode. The two 8-bit
counters are concatenated to form a sin-
gle 16-bit counter. The counter may be
started or stopped with the lower of the
two TxRUN bits, i.e. T1RUN, T3RUN,
T5RUN, and T7RUN. The TIOx pins will
FF FFA4h
Duty Cycle/Capture 4
Register
function as PWM outputs.
11 – Capture Mode. Both 8-bit counters are
concatenated and operate as a single
16-bit counter. The counter may be start-
ed or stopped with the lower of the two
TxRUN bits, i.e., T1RUN, T3RUN,
T5RUN, and T7RUN. The TIOx pins will
function as capture inputs.
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