CP3BT23 Datasheet, PDF (130/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

The ideal required prescaler value P_ideal can be calculated
as follows:
SFS
SRCLK
(auxiliary
frame sync)
SRFS
(auxiliary
frame sync)
P_ideal = f_{Audio In} / f_bit = 12 MHz / 256 kHz = 46.875
Therefore, the real prescaler value is 47. This results in a bit
clock error equal to:
f_{bit_error} = (f_bit - f_{Audio In}/P_real) / f_bit × 100
= (256 kHz - 12 MHz/47) / 256 kHz × 100 = 0.27%
19.4 FRAME CLOCK GENERATION
STD/SRD
Data from/to Data from/to Data from/to
Codec 1 Codec 2 Codec 3
The clock for the frame synchronization signals is derived
from the bit clock of the audio interface. A 7-bit prescaler is
Slot 0
Slot 1
Slot 2
Slot 3
used to divide the bit clock to generate the frame sync clock
for the receive and transmit operations. The bit clock is di-
Frame
vided by FCPRS + 1. In other words, the value software
DS057
Figure 67. Accessing Three Devices in Network Mode
19.3 BIT CLOCK GENERATION
An 8-bit prescaler is provided to divide the audio interface
input clock down to the required bit clock rate. Software can
te ^{choose between two input clock sources, a primary and a}
secondary clock source.
On the CP3BT23, the two optional input clock sources are
the 12-MHz Aux1 clock (also used for the Bluetooth LLC)
and the 48-MHz PLL output clock. The input clock is divided
by the value of the prescaler BCPRS[7:0] + 1 to generate
le ^{the bit clock.}
The bit clock rate f_bit can be calculated by the following
equation:
f_bit = n × f_Sample × Data Length
n = Number of Slots per Frame
o _{fSample = Sample Frequency in Hz}
Data Length = Length of data word in multiples of 8 bits
The ideal required prescaler value P_ideal can be calculated
s as follows:
P_ideal = f_{Audio In} / f_bit
The real prescaler must be set to an integer value, which
b ^{should be as close as possible to the ideal prescaler value,}
to minimize the bit clock error, f_{bit_error}.
f_{bit_error} [%] = (f_bit - f_{Audio In}/P_real) / f_bit × 100
Example:
O ^{The audio interface is used to transfer 13-bit linear PCM}
must write into the ACCR.FCPRS field is equal to the bit
number per frame minus one. The frame may be longer than
the valid data word but it must be equal to or larger than the
8- or 16-bit word. Even if 13-, 14-, or 15-bit data is being
used, the frame width must always be at least 16 bits wide.
In addition, software can specify the length of a long frame
sync signal. A long frame sync signal can be either 6, 13,
14, 15, or 16 bits long, depending on the external codec be-
ing used. The frame sync length can be configured by the
Frame Sync Length field (FSL) in the AGCR register.
19.5 AUDIO INTERFACE OPERATION
19.5.1 Clock Configuration
The Aux1 clock (generated by the Clock module described
in Section 11.9) must be configured, because it is the time
base for the AAI module. Software must write an appropri-
ate divisor to the ACDIV1 field of the PRSAC register to pro-
vide a 12 MHz input clock. Software also must enable the
Aux1 clock by setting the ACE1 bit in the CRCTRL register.
For example:
PRSAC &= 0xF0;
// Set Aux1 prescaler to 1 (F = 12 MHz)
CRCTRL |= ACE1; // Enable Aux1 clk
19.5.2 Interrupts
The interrupt logic of the AAI combines up to four interrupt
sources and generates one interrupt request signal to the
Interrupt Control Unit (ICU).
The four interrupt sources are:
! RX FIFO Overrun - ASCR.RXEIP = 1
! RX FIFO Almost Full (Warning Level) - ASCR.RXIP = 1
data for one audio channel at a sample rate of 8k samples _{! TX FIFO Under run - ASCR.TXEIP = 1}
per second. The input clock of the audio interface is 12 MHz. _{! TX FIFO Almost Empty (Warning Level) - ASCR.TXIP=1}
Furthermore, the codec requires a minimum bit clock of 256
kHz to operate properly. Therefore, the number of slots per ^{In addition to the dedicated input to the ICU for handling}
frame must be set to 2 (network mode) although actually ^{these interrupt sources, the Serial Frame Sync (SFS) signal}
only one slot (slot 0) is used. The codec and the audio inter- ^{is an input to the MIWU (see Section 13.0), which can be}
face will put their data transmit pins in TRI-STATE mode af- ^{programmed to generate edge-triggered interrupts.}
ter the PCM data word has been transferred. The required
bit clock rate f_bit can be calculated by the following equation:
f_bit = n × f_Sample × Data Length = 2 × 8 kHz × 16 = 256 kHz
129
www.national.com