CP3BT23 Datasheet, PDF (166/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

Acknowledge Cycle
Addressing Transfer Formats
The Acknowledge Cycle consists of two signals: the ac- Each device on the bus has a unique address. Before any
knowledge clock pulse the master sends with each byte data is transmitted, the master transmits the address of the
transferred, and the acknowledge signal sent by the receiv- slave being addressed. The slave device should send an
ing device (Figure 91).
acknowledge signal on the SDA signal, once it recognizes
its address.
Acknowledgment
Signal from Receiver
The address is the first seven bits after a Start Condition.
SDA
MSB
The direction of the data transfer (R/W) depends on the bit
sent after the address (the eighth bit). A low-to-high transi-
tion during a SCL high period indicates the Stop Condition,
SCL
1 2 3-6 7 8 9
1 2 3-8 9
and ends the transaction (Figure 93).
S
ACK
ACK
P
Start
Stop
Condition
Condition
Byte Complete
Clock Line Held
SDA
Interrupt Within
Low by Receiver
Receiver
While Interrupt
is Serviced
DS077
Figure 91. ACCESS.bus Data Transaction
The master generates the acknowledge clock pulse on the
ninth clock pulse of the byte transfer. The transmitter releas-
es the SDA line (permits it to go high) to allow the receiver
to send the acknowledge signal. The receiver must pull
te ^{down the SDA line during the acknowledge clock pulse,}
which signals the correct reception of the last data byte, and
its readiness to receive the next byte. Figure 92 illustrates
the acknowledge cycle.
Data Output
by Transmitter
le ^{Data Output}
by Receiver
Transmitter Stays Off
the Bus During the
Acknowledgment Clock
Acknowledgment
Signal from Receiver
SCL
S
1 2 3-6 7 8 9
o _Start
Condition
DS078
Figure 92. ACCESS.bus Acknowledge Cycle
s _{The master generates an acknowledge clock pulse after}
each byte transfer. The receiver sends an acknowledge sig-
nal after every byte received. There are two exceptions to
the “acknowledge after every byte” rule.
b ! When the master is the receiver, it must indicate to the
transmitter an end-of-data condition by not-acknowledg-
ing (“negative acknowledge”) the last byte clocked out of
the slave. This “negative acknowledge” still includes the
acknowledge clock pulse (generated by the master), but
O ^{the SDA line is not pulled down.}
SCL
S
1-7 8 9
Address R/W ACK
1-7 8 9
Data
ACK
1-7 8 9
P
Data
ACK
Start
Condition
Stop
Condition
DS079
Figure 93. A Complete ACCESS.bus Data Transaction
When the address is sent, each device in the system com-
pares this address with its own. If there is a match, the de-
vice considers itself addressed and sends an acknowledge
signal. Depending upon the state of the R/W bit (1 = read,
0 = write), the device acts as a transmitter or a receiver.
The ACCESS.bus protocol allows sending a general call ad-
dress to all slaves connected to the bus. The first byte sent
specifies the general call address (00h) and the second byte
specifies the meaning of the general call (for example,
“Write slave address by software only”). Those slaves that
require the data acknowledge the call and become slave re-
ceivers; the other slaves ignore the call.
Arbitration on the Bus
Arbitration is required when multiple master devices attempt
to gain control of the bus simultaneously. Control of the bus
is initially determined according to address bits and clock
cycle. If the masters are trying to address the same bus de-
vice, data comparisons determine the outcome of this arbi-
tration. In master mode, the device immediately aborts a
transaction if the value sampled on the SDA lines differs
from the value driven by the device. (Exceptions to this rule
are SDA while receiving data; in these cases the lines may
be driven low by the slave without causing an abort.)
The SCL signal is monitored for clock synchronization and
! When the receiver is full, otherwise occupied, or a prob- _{allows the slave to stall the bus. The actual clock period will}
lem has occurred, it sends a negative acknowledge to in- _{be the one set by the master with the longest clock period}
dicate that it cannot accept additional data bytes.
or by the slave stall period. The clock high period is deter-
mined by the master with the shortest clock high period.
When an abort occurs during the address transmission, the
master that identifies the conflict should give up the bus,
switch to slave mode, and continue to sample SDA to see if
it is being addressed by the winning master on the AC-
CESS.bus.
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