CP3BT23 Datasheet, PDF (171/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

GCMTCH
TSDA
TGSCL
The Global Call Match bit is set in slave mode 23.3.4 ACB Control Register 1 (ACBCTL1)
when the ACBCTL1.GCMEN bit is set and the
address byte (the first byte transferred after a
Start Condition) is 00h. It is cleared by a Start
Condition or repeated Start and Stop Condi-
tion (including illegal Start or Stop Condition).
The ACBCTL1 register is a byte-wide, read/write register
that configures and controls the ACB module. When reset,
disabled, or in Halt or Idle modes, the ACBCTL1 register is
cleared.
0 – No global call match occurred.
1 – Global call match occurred.
7
6
5 43 2 1 0
The Test SDA bit samples the state of the SDA _{STASTRE NMINTE GCMEN ACK Res. INTEN STOP START}
signal. This bit can be used while recovering
from an error condition in which the SDA sig-
nal is constantly pulled low by a slave that _START
The Start bit is set to generate a Start Condi-
went out of sync. This bit is a read-only bit.
tion on the ACCESS.bus. The START bit is
Data written to it is ignored.
cleared when the Start Condition is sent, or
The Toggle SCL bit enables toggling the SCL
upon detection of a Bus Error
signal during error recovery. When the SDA
signal is low, writing 1 to this bit drives the SCL
signal high for one cycle. Writing 1 to TGSCL
when the SDA signal is high is ignored. The bit
is cleared when the clock toggle is completed.
0 – Writing 0 has no effect.
1 – Writing 1 toggles the SDA signal high for
one cycle.
Obsolete ^STOP
(ACBST.BER = 1). This bit should be set only
when in Master mode, or when requesting
Master mode. If this device is not the active
master of the bus (ACBST.MASTER = 0), set-
ting the START bit generates a Start
Con0dition as soon as the ACCESS.bus is
free (ACBCST.BB = 0). An address send se-
quence should then be performed. If this de-
vice is the active master of the bus
(ACBST.MASTER = 1), when the START bit is
set, a write to the ACBSDA register generates
a Start Condition, then the ACBSDA data is
transmitted as the slave’s address and the re-
quested transfer direction. This case is a re-
peated Start Condition. It may be used to
switch the direction of the data flow between
the master and the slave, or to choose anoth-
er slave device without using a Stop Condition
in between.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Start condition.
The Stop bit in master mode generates a Stop
Condition that completes or aborts the current
message transfer. This bit clears itself after
the Stop condition is issued.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Stop condition.
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