CP3BT23 Datasheet, PDF (189/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

25.5.8 Timer Interrupt Control Register (TICTL)
TBIEN
The Timer Interrupt B Enable bit controls
The TICTL register is a byte-wide, read/write register that
contains the interrupt enable bits and interrupt pending bits
for the four timer interrupt sources, designated A, B, C, and
D. The condition that causes each type of interrupt depends
on the operating mode, as shown in Table 70.
This register is cleared upon reset. The register format is _TCIEN
shown below.
whether an interrupt is generated on each oc-
currence of interrupt condition B. For an ex-
planation of interrupt conditions A, B, C, and
D, see Table 70.
0 – Condition B interrupts disabled.
1 – Condition B interrupts enabled.
The Timer Interrupt C Enable bit controls
whether an interrupt is generated on each oc-
currence of interrupt condition C. For an ex-
7
6
54
3
2
1
0
TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND
planation of interrupt conditions A, B, C, and
D, see Table 70.
0 – Condition C interrupts disabled.
1 – Condition C interrupts enabled.
TAPND
TBPND
TCPND
TDPND
TAIEN
The Timer Interrupt Source A Pending bit indi-
cates that timer interrupt condition A has oc-
curred. For an explanation of interrupt
conditions A, B, C, and D, see Table 70. This
bit can be set by hardware or by software. To
clear this bit, software must use the Timer In-
terrupt Clear Register (TICLR). Attempting to
directly write a 0 to this bit is ignored.
te ^{0 – Interrupt source A has not triggered.}
1 – Interrupt source A has triggered.
The Timer Interrupt Source B Pending bit indi-
cates that timer interrupt condition B has oc-
curred. For an explanation of interrupt
conditions A, B, C, and D, see Table 70. This
le ^{bit can be set by hardware or by software. To}
clear this bit, software must use the Timer In-
terrupt Clear Register (TICLR). Attempting to
directly write a 0 to this bit is ignored.
0 – Interrupt source B has not triggered.
1 – Interrupt source B has triggered.
o ^{The Timer Interrupt Source C Pending bit in-}
dicates that timer interrupt condition C has oc-
curred. For an explanation of interrupt
conditions A, B, C, and D, see Table 70. This
s ^{bit can be set by hardware or by software. To}
clear this bit, software must use the Timer In-
terrupt Clear Register (TICLR). Attempting to
directly write a 0 to this bit is ignored.
0 – Interrupt source C has not triggered.
b _{1 – Interrupt source C has triggered.}
The Timer Interrupt Source D Pending bit in-
dicates that timer interrupt condition D has oc-
curred. For an explanation of interrupt
O^{conditions A, B, C, and D, see Table 70. This}
TDIEN
The Timer Interrupt D Enable bit controls
whether an interrupt is generated on each oc-
currence of interrupt condition D. For an ex-
planation of interrupt conditions A, B, C, and
D, see Table 70.
0 – Condition D interrupts disabled.
1 – Condition D interrupts enabled.
25.5.9 Timer Interrupt Clear Register (TICLR)
The TICLR register is a byte-wide, write-only register that al-
lows software to clear the TAPND, TBPND, TCPND, and
TDPND bits in the Timer Interrupt Control (TICTRL) regis-
ter. Do not modify this register with instructions that access
the register as a read-modify-write operand, such as the bit
manipulation instructions. The register reads as FFh. The
register format is shown below.
7
4
3
2
1
0
Reserved
TDCLR TCCLR TBCLR TACLR
TACLR
TBCLR
TCCLR
The Timer Pending A Clear bit is used to clear
the Timer Interrupt Source A Pending bit
(TAPND) in the Timer Interrupt Control regis-
ter (TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TAPND bit.
The Timer Pending A Clear bit is used to clear
the Timer Interrupt Source B Pending bit (TB-
PND) in the Timer Interrupt Control register
(TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TBPND bit.
The Timer Pending C Clear bit is used to clear
bit can be set by hardware or by software. To
the Timer Interrupt Source C Pending bit
clear this bit, software must use the Timer In-
(TCPND) in the Timer Interrupt Control regis-
terrupt Clear Register (TICLR). Attempting to
ter (TICTL).
directly write a 0 to this bit is ignored.
0 – Writing a 0 has no effect.
0 – Interrupt source D has not triggered.
1 – Writing a 1 clears the TCPND bit.
1 – Interrupt source D has triggered.
TDCLR
The Timer Pending D Clear bit is used to clear
The Timer Interrupt A Enable bit controls
the Timer Interrupt Source D Pending bit (TD-
whether an interrupt is generated on each oc-
PND) in the Timer Interrupt Control register
currence of interrupt condition A. For an ex-
(TICTL).
planation of interrupt conditions A, B, C, and
0 – Writing a 0 has no effect.
D, see Table 70.
1 – Writing a 1 clears the TDPND bit.
0 – Condition A interrupts disabled.
1 – Condition A interrupts enabled.
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