CP3BT23 Datasheet, PDF (182/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

25.2.1 Mode 1: Processor-Independent PWM
The timer can be configured to toggle the TA output bit on
Mode 1 is the Processor-Independent Pulse Width Modula- ^{each underflow. This generates a clock signal on the TA out-}
tion (PWM) mode, which generates pulses of a specified ^{put with the width and duty cycle determined by the values}
width and duty cycle, and which also provides a separate ^{stored in the TCRA and TCRB registers. This is a “proces-}
general-purpose timer/counter.
sor-independent” PWM clock because once the timer is set
up, no more action is required from the CPU to generate a
Figure 98 is a block diagram of the Multi-Function Timer _{continuous PWM signal.}
configured to operate in Mode 1. Timer/Counter 1 (TCNT1)
functions as the time base for the PWM timer. It counts ^{The timer can be configured to generate separate interrupts}
down at the clock rate selected for the counter. When an un- ^{upon reload from the TCRA and TCRB registers. The inter-}
derflow occurs, the timer register is reloaded alternately ^{rupts can be enabled or disabled under software control.}
from the TCRA and TCRB registers, and counting proceeds ^{The CPU can determine the cause of each interrupt by look-}
downward from the loaded value.
ing at the TAPND and TBPND bits, which are updated by
the hardware on each occurrence of a timer reload.
On the first underflow, the timer is loaded from the TCRA
register, then from the TCRB register on the next underflow, ^{In Mode 1, Timer/Counter 2 (TCNT2) can be used either as}
then from the TCRA register again on the next underflow,
and so on. Every time the counter is stopped and restarted,
it always obtains its first reload value from the TCRA regis-
ter. This is true whether the timer is restarted upon reset, af-
ter entering Mode 1 from another mode, or after stopping
and restarting the clock with the Timer/Counter 1 clock se-
lector.
a simple system timer, an external event counter, or a pulse-
accumulate counter. The clock counts down using the clock
selected with the Timer/Counter 2 clock selector. It gener-
ates an interrupt upon each underflow if the interrupt is en-
abled with the TDIEN bit.
lete ^{Timer 1}
o ^Clock
Reload A = Time 1
TCRA
Underflow
Timer/Counter 1
TCNT1
Underflow
Reload B = Time 2
TCRB
TAPND
TAIEN
TAEN
TBIEN
TBPND
Timer
Interrupt A
TA
Timer
Interrupt B
s Timer 2
Clock
b_Clock
O^Selector
Timer/Counter 2
TCNT2
TDIEN
TDPND
Timer
Interrupt D
TB
DS084
Figure 98. Processor-Independent PWM Mode
181
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