CP3BT23 Datasheet, PDF (196/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

IxCEN
The Timer x Interrupt C Enable bit controls in- IxDPD
The Timer x Interrupt D Pending bit indicates
terrupt requests triggered on the correspond-
that an interrupt condition for the related timer
ing IxCPD bit being set. The associated
subsystem has occurred. Table 73 on page
IxCPD bit will be updated regardless of the
192 lists the hardware condition which causes
value of the IxCEN bit.
this bit to be set.
0 – Disable system interrupt request for the
0 – No interrupt pending.
IxCPD pending bit.
1 – Timer interrupt condition occurred.
1 – Enable system interrupt request for the Ix-
CPD pending bit.
26.2.6
Clock Prescaler Register 1 (CLK1PS)
IxDEN
Timer x Interrupt D Enable bit controls inter- The CLK1PS register is a word-wide read/write register.
rupt requests triggered on the corresponding ^{The register is split into two 8-bit fields called C1PRSC and}
IxDPD bit being set. The associated IxDPD bit C2PRSC. Each field holds the 8-bit clock prescaler com-
will be updated regardless of the value of the pare value for timer subsystems 1 and 2 respectively. The
IxDEN bit.
register is cleared at reset.
0 – Disable system interrupt request for the
IxDPD pending bit.
15
8
7
0
1 – Enable system interrupt request for the
IxDPD pending bit.
C2PRSC
C1PRSC
26.2.5 Interrupt Pending Register (INTPND)
The INTPND register is a word-wide read/write register
which contains all 16 interrupt pending bits. There are four
interrupt pending bits called IxAPD through IxDPD for each
te ^{timer subsystem. Each interrupt pending bit is set by a hard-}
ware event and can be cleared if software writes a 1 to the
bit position. The value will remain unchanged if a 0 is written
to the bit position. All interrupt pending bits are cleared (0)
upon reset.
C1PRSC
C2PRSC
le ⁷
6
5
4
3
2
1
0
I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD
15 14 13 12 11 10 9
8
The Clock Prescaler 1 Compare Value field
holds the 8-bit prescaler value for timer sub-
system 1. The counter of timer subsystem is
incremented each time when the clock pres-
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C1PRSC + 1). For example, 00h is a
ratio of 1, and FFh is a ratio of 256.
The Clock Prescaler 2 Compare Value field
holds the 8-bit prescaler value for timer sub-
system 2. The counter of timer subsystem is
incremented each time when the clock pres-
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C2PRSC + 1).
o _{I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD 26.2.7 Clock Prescaler Register 2 (CLK2PS)}
IxAPD
Obs ^IxBPD
The Timer x Interrupt A Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 73 on page
192 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
The Timer x Interrupt B Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 73 on page
192 lists the hardware condition which causes
The Clock Prescaler Register 2 (CLK2PS) is a word-wide
read/write register. The register is split into two 8-bit fields
called C3PRSC and C4PRSC. Each field holds the 8-bit
clock prescaler compare value for timer subsystems 3 and
4 respectively. The register is cleared at reset.
15
8
7
0
C4PRSC
C3PRSC
C3PRSC The Clock Prescaler 3 Compare Value field
holds the 8-bit prescaler value for timer sub-
this bit to be set.
system 3. The counter of timer subsystem is
0 – No interrupt pending.
incremented each time when the clock pres-
1 – Timer interrupt condition occurred.
caler compare value matches the value of the
IxCPD
The Timer x Interrupt C Pending bit indicates
clock prescaler counter. The division ratio is
that an interrupt condition for the related timer
equal to (C3PRSC + 1).
subsystem has occurred. Table 73 on page _{C4PRSC The Clock Prescaler 4 Compare Value field}
192 lists the hardware condition which causes
holds the 8-bit prescaler value for timer sub-
this bit to be set.
system 4. The counter of timer subsystem is
0 – No interrupt pending.
incremented each time when the clock pres-
1 – Timer interrupt condition occurred.
caler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C4PRSC + 1).
195
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