CP3BT23 Datasheet, PDF (28/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

IPRE
The Preliminary Idle bit controls whether an IPST
The Post Idle bit controls whether an idle cycle
idle cycle is inserted prior to the current bus
follows the current bus cycle, when the next
cycle, when the new bus cycle accesses a dif-
bus cycle accesses a different zone.
ferent zone. No idle cycles are required for on-
0 – No idle cycle.
chip accesses.
1 – Idle cycle inserted.
0 – No idle cycle (recommended).
IPRE
The Preliminary Idle bit controls whether an
1 – Idle cycle inserted.
idle cycle is inserted prior to the current bus
6.4.4 Static Zone 1 Configuration Register (SZCFG1)
cycle, when the new bus cycle accesses a dif-
ferent zone.
The SZCFG1 register is a word-wide, read/write register
0 – No idle cycle.
that controls the timing and bus characteristics for off-chip
1 – Idle cycle inserted.
accesses selected with the SEL1 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
6.4.5 Static Zone 2 Configuration Register (SZCFG2)
The SZCFG2 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
7
BW
15
WAIT
HOLD
RBE
WBR
BW
6
5
WBR RBE
4
3
HOLD
2
0
WAIT
accesses selected with the SEL2 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
Reserved
12 11 10 9
8
FRE IPRE IPST Res.
7
6
5
BW WBR RBE
4
3
HOLD
2
0
WAIT
te The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
le ^{seven additional TIW wait cycles. These bits}
are ignored if the SZCFG1.FRE bit is set.
The Memory Hold field specifies the number
of Thold clock cycles used for each memory
access, ranging from 00b for no Thold cycles
to 11b for three Thold clock cycles. These bits
o ^{are ignored if the SZCFG1.FRE bit is set.}
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
s ^{the SZCFG1.FRE bit is set or the}
SZCFG1.BW is clear.
0 – Burst read disabled.
1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait
b _{state is added on burst read transaction. This}
bit is ignored, when SZCFG1.FRE bit is set or
when SZCFG1.RBE is clear.
0 – No TBW on burst read cycles.
O^{1 – One TBW on burst read cycles.}
15
WAIT
HOLD
RBE
WBR
Reserved
12 11 10 9
8
FRE IPRE IPST Res.
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Memory Hold field specifies the number
of Thold clock cycles used for each memory
access, ranging from 00b for no Thold cycles
to 11b for three Thold clock cycles. These bits
are ignored if the SZCFG2.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG2.FRE bit is set or the
SZCFG2.BW is clear.
0 – Burst read disabled.
1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
The Bus Width bit controls the bus width of the
bit is ignored, when SZCFG2.FRE bit is set or
zone.
when SZCFG2.RBE is clear.
0 – 8-bit bus width.
0 – No TBW on burst read cycles.
1 – 16-bit bus width.
1 – One TBW on burst read cycles.
FRE
The Fast Read Enable bit controls whether BW
The Bus Width bit controls the bus width of the
fast read bus cycles are used. A fast read op-
zone.
eration takes one clock cycle. A normal read
0 – 8-bit bus width.
operation takes at least two clock cycles.
1 – 16-bit bus width.
0 – Normal read cycles.
1 – Fast read cycles.
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