CP3BT23 Datasheet, PDF (102/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

Bus
Signal
CAN
Clock
PREVIOUS
BIT
A
e
TSEG1
"NORMAL" BIT TIME
TSEG2
NEXT BIT
PREVIOUS
BIT
A
TSEG1
SJW
TSEG2
NEXT BIT
BIT TIME LENGTHENED BY SJW
Figure 43. Resynchronization (e > SJW)
DS029
te _Bus
Signal
CAN
Clock
le PREVIOUS
BIT
A
e
TSEG1
"NORMAL" BIT TIME
TSEG2
o PREVIOUS
BIT
A
TSEG1
TSEG2
BIT TIME SHORTENED BY SJW
NEXT BIT
DS030
s_{Figure 44. Resynchronization (e < -SJW)}
18.2.7 Clock Generator
The CAN prescaler (PSC) is shown is Figure 45. It divides
b _{the CKI input clock by the value defined in the CTIM register.}
The resulting clock is called time quanta clock and defines
the length of one time quantum (tq).
Please refer to CAN Timing Register (CTIM) on page 118
O ^{for a detailed description of the CTIM register.}
PSC = PSC[5:0] + 2
TSEG1 = TSEG1[3:0] + 1
TSEG2 = TSEG2[2:0] + 1
CKI
÷ PSC
÷ (1+TSEG1+TSEG2)
Internal Time
Note: PSC is the value of the clock prescaler. TSEG1 and
Quanta Clock (1/tq)
TSEG2 are the length of time segment 1 and 2 in time quan-
ta.
Figure 45. CAN Prescaler
Bit Rate
DS031
The resulting bus clock can be calculated by the equation: 18.3 MESSAGE TRANSFER
busclock = --------------------------------------C----K-----I-------------------------------------
(PSC)x(1 + TSEG1 + TSEG2)
The values of PSC, TSEG1, and TSEG2 are specified by
the contents of the registers PSC, TSEG1, and TSEG2 as
follows:
The CAN module has access to 15 independent message
buffers, which are memory mapped in RAM. Each message
buffer consists of 8 different 16-bit RAM locations and can
be individually configured as a receive message buffer or as
a transmit message buffer.
A dedicated acceptance filtering procedure enables soft-
ware to configure each buffer to receive only a single mes-
sage ID or a group of messages. One buffer uses an
101
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