CP3BT23 Datasheet, PDF (234/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

29.10 MICROWIRE/SPI TIMING
Table 81 Microwire/SPI Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
Microwire/SPI Input Signals
t_MSKh
t_MSKl
t_MSKp
118 Microwire Clock High
118 Microwire Clock Low
118
Microwire Clock Period
119
At 2.0V (both edges)
80
-
At 0.8V (both edges)
80
-
SCIDL bit = 0; Rising Edge
(RE) MSK to next RE MSK
-
200
SCIDL bit = 1; Falling Edge
(FE) MSK to next FE MSK
-
t_MSKh
t_MSKs
t_MWCSh
t_MWCSs
t_MDIh
t_MDIs
t_MSKh
t_MSKl
t_MSKp
118
118
118
119
118
119
118
120
118
120
118
120
118
118
118
MSK Hold (slave only)
MSK Setup (slave only)
After MWCS goes inactive
40
Before MWCS goes active
80
MWCS Hold (slave only)
SCIDL bit = 0: After FE
MSK
40
SCIDL bit = 1: After RE
MSK
te ^{MWCS Setup (slave only)}
SCIDL bit = 0: Before RE
MSK
80
SCIDL bit = 1: Before FE
MSK
Normal Mode: After RE
le ^MSK
Microwire Data In Hold (master)
0
Alternate Mode: After FE
MSK
Normal Mode: After RE
MSK
Microwire Data In Hold (slave)
40
o^{Alternate Mode: After FE}
MSK
s Microwire Data In Setup
Normal Mode: Before RE
MSK
80
Alternate Mode: Before FE
MSK
Microwire/SPI Output Signals
b _{Microwire Clock High}
At 2.0V (both edges)
40
Microwire Clock Low
O^{Microwire Clock Period}
At 0.8V (both edges)
40
SCIDL bit = 0: Rising Edge
(RE) MSK to next RE MSK
100
119
SCIDL bit = 1: Falling Edge
(FE) MSK to next FE MSK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t_MSKd
t_MDOf
118
MSK Leading Edge Delayed (master
only)
Data Out Bit #7 Valid
118
Microwire Data Float ^b
(slave only)
After RE on MWCS
0.5 t_MSK
-
1.5 t_MSK
25
118
Normal Mode: After FE
MSK
-
t_MDOh
Microwire Data Out Hold
119
0.0
Alternate Mode: After RE
MSK
t_MDOnf 122 Microwire Data No Float (slave only) After FE on MWCS
0
25
233
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