CP3BT23 Datasheet, PDF (58/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

11.9.2 High Frequency Clock Prescaler Register
(PRSFC)
11.9.3 Low Frequency Clock Prescaler Register
(PRSSC)
The PRSFC register is a byte-wide read/write register that
holds the 4-bit clock divisor used to generate the high-fre-
quency clock. In addition, the upper three bits are used to
control the operation of the PLL. The register is initialized to
4Fh at reset (except in PROG mode.)
The PRSSC register is a byte-wide read/write register that
holds the clock divisor used to generate the Slow Clock from
the Main Clock. The register is initialized to B6h at reset.
7
0
7
6
4
3
0
SCDIV
Res
FCDIV
MODE
MODE
FCDIV
SCDIV
The Slow Clock Divisor field specifies a divi-
sor to be used when generating the Slow
The Fast Clock Divisor specifies the divisor
Clock from the Main Clock. The Main Clock is
used to obtain the high-frequency System
divided by a value of (2 × (SCDIV + 1)) to ob-
Clock from the PLL or Main Clock. The divisor
is (FCDIV + 1).
The PLL MODE field specifies the operation
mode of the on-chip PLL. After reset the
MODE bits are initialized to 100b, so the PLL
is configured to generate a 48-MHz clock.
This register must not be modified when the
te ^{System Clock is derived from the PLL Clock.}
The System Clock must be derived from the
low-frequency oscillator clock while the
MODE field is modified.
tain the Slow Clock. At reset, the SCDIV reg-
ister is initialized to B6h, which generates a
Slow Clock rate of 32786.885 Hz. This is
about 0.5% faster than a Slow Clock generat-
ed from an external 32768 Hz crystal network.
11.9.4 Auxiliary Clock Prescaler Register (PRSAC)
The PRSAC register is a byte-wide read/write register that
holds the clock divisor values for prescalers used to gener-
ate the two auxiliary clocks from the Main Clock. The regis-
ter is initialized to FFh at reset.
Output
7
4
3
0
le ^MODE2:0
Frequency
(from 12 MHz
Description
ACDIV2
ACDIV2
input clock)
000 Reserved
001 Reserved
o _{010 Reserved}
011 36 MHz
s ^{100 48 MHz}
101 60 MHz
Reserved
Reserved
Reserved
3× Mode
4× Mode
5× Mode
ACDIV1
ACDIV2
The Auxiliary Clock Divisor 1 field specifies
the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock
is divided by a value of (ACDIV1 + 1).
The Auxiliary Clock Divisor 2 field specifies
the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock
is divided by a value of (ACDIV2 + 1).
110 Reserved
Reserved
Ob ^{111 Reserved}
Reserved
57
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