CP3BT23 Datasheet, PDF (239/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

29.11 ACCESS.BUS TIMING
Table 82 ACCESS.bus Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
ACCESS.bus Input Signals
t_BUFi
124
Bus free time between Stop and Start
Condition
t_SCLhigho
-
t_CSTOsi 124 SCL setup time
Before Stop Condition
(8 × t_CLK) - t_SCLri
-
t_CSTRhi 124 SCL hold time
After Start Condition
(8 × t_CLK) - t_SCLri
-
t_CSTRsi 124 SCL setup time
Before Start Condition
(8 × t_CLK) - t_SCLri
-
t_DHCsi
t_DLCsi
t_SCLfi
t_SCLri
t_SCLlowi
t_SCLhighi
t_SDAri
t_SDAfl
t_SDAhi
t_SDAsi
t_BUFo
t_CSTOso
t_CSTRho
t_CSTRso
t_DHCso
t_DLCso
t_SCLfo
t_SCLro
t_SCLlowo
t_SCLhigho
t_SDAfo
t_SDAro
125
124
123
123
126
126
123
123
126
126
124
124
124
125
125
124
123
123
126
126
123
123
Data High setup time
Data Low setup time
SCL signal rise time
SCL signal fall time
SCL low time
te ^{SCL high time}
Before SCL Rising Edge
(RE)
Before SCL RE
After SCL Falling Edge
(FE)
After SCL RE
SDA signal rise time
SDA signal fall time
SDA hold time
After SCL FE
SDA setup time
Before SCL RE
le ^{ACCESS.bus Output Signals}
Bus free time between Stop and Start
Condition
SCL setup time
Before Stop Condition
o _{SCL hold time}
After Start Condition
SCL setup time
Data High setup time
s _{Data Low setup time}
Before Start Condition
Before SCL R.E.
Before SCL R.E.
SCL signal Fall time
SCL signal Rise time
b _{SCL low time}
After SCL F.E.
SCL high time
SDA signal Fall time
O^{SDA signal Rise time}
After SCL R.E.
2 × t_CLK
2 × t_CLK
-
-
16 × t_CLK
16 × t_CLK
-
-
0
2 × t_CLK
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho
t_SCLhigho -t_SDAro
t_SCLhigho -t_SDAfo
-
-
(K × t_CLK) -1^e
(K × t_CLK) -1^e
-
-
-
-
300
1000
-
-
1000
300
-
-
-
-
-
-
-
-
300^c
-^d
-
-
300
-
t_SDAho 126 SDA hold time
After SCL F.E.
(7 × t_CLK) - t_SCLfo
-
t_SDAvo 126 SDA valid time
After SCL F.E.
(7 × t_CLK) + t_RD
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