CP3BT23 Datasheet, PDF (56/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

11.8.2 Manual and SDI External Reset
11.8.3 Fault-Tolerant External Reset
An external reset circuit based on the LM3724 5-Pin Micro-
processor Reset Circuit is shown in Figure 9. The LM3724
produces a 190-ms logic low reset pulse when the power
supply rises above a threshold voltage or a manual reset
button is pressed. Various reset thresholds are available for
the LM3724, however the option for 3.08V is most suitable
for a CP3BT23 device operating from an IOVCC at 3.3V.
An external reset circuit based on the LM3710 Microproces-
sor Supervisory Circuit is shown in Figure 10. It provides a
high level of fault tolerance in that it provides the ability to
monitor both the VCC supply for the core logic and the IO-
VCC supply. It also provides a low-voltage indication for the
IOVCC supply and an external watchdog timer.
IOVCC
Core VCC
(2.5V)
IOVCC
IOVCC
IOVCC
VCC
CP3BT2x
278k Ω
10k Ω
CP3BT2x
Reset Output
Manual
Reset
LM3724
5-Pin Reset
Circuit
te ^{SDI Reset}
RESET
GND
DS497
Power Fail
Input (PFI)
332k Ω
Manual
Reset
LM3710
Supervisory
Power Fail Output (PFO)
Circuit with
Power-Fail
Low Line Output (LLO)
and Low-Line
Detection
Watchdog Input (WDI)
RESET
NMI
IRQ
GPIO
GND
DS498
Figure 9. Manual and SDI External Reset
The LM3724 provides a debounced input for a manual
pushbutton reset switch. It also has an open-drain output
which can be used for implementing a wire-OR connection
with a reset signal from a serial debug interface. This circuit
le ^{is typical of a design to be used in a development or evalu-}
ation environment, however it is a good recommendation for
all general CP3BT23 designs. If an SDI interface is not im-
Obso ^{plemented, an LM3722 with active pullup may be used.}
Figure 10. Fault-Tolerant External Reset
The signals shown in Figure 10 are:
! Core VCC—the 2.5V power supply rail for the core logic.
! IOVCC—the 2.5–3.3V power supply rail for the I/O logic.
! Watchdog Input (WDI)—this signal is asserted by the
CP3BT23 at regular intervals to indicate normal opera-
tion. A general-purpose I/O (GPIO) port may be used to
provide this signal. If the internal watchdog timer in the
CP3BT23 is used, then the LM3704 Microprocessor Su-
pervisory Circuit can provide the same features as the
LM3710 but without the watchdog timer.
! RESET—an active-low reset signal to the CP3BT23.
The LM3710 is available in versions with active pullup or
an open-drain RESET output.
! Power-Fail Input (PFI)—this is a voltage level derived
from the Core VCC power supply rail through a simple
resistor divider network.
! Power-Fail Output (PFO)—this signal is asserted when
the voltage on PFI falls below 1.225V. PFO is connected
to the non-maskable interrupt (NMI) input on the
CP3BT23. A system shutdown routine can then be in-
voked by the NMI handler.
! Low Line Output (LLO)—this signal is asserted when the
main IOVCC level fails below a warning threshold voltage
but remains above a reset detection threshold. This sig-
nal may be routed to the NMI input on the CP3BT23 or
to a separate interrupt input.
These additional status and feedback mechanisms allow
the CP3BT23 to recover from software hangs or perform
system shutdown functions before being placed into reset.
The standard reset threshold for the LM3710 is 3.08V with
other options for different watchdog timeout and reset time-
outs. The selection of these values are much more applica-
tion-specific. The combination of a watchdog timeout period
of 1600 ms and a reset period of 200 ms is a reasonable
starting point.
55
www.national.com