CP3BT23 Datasheet, PDF (193/260 Pages) Texas Instruments – CP3BT23 Reprogrammable Connectivity Processor with Bluetooth and Dual CAN Interfaces

Figure 106 illustrates the configuration of a timer subsystem
while operating in capture mode. The numbering in
Figure 106 refers to timer subsystem 1 but equally applies
to the other three timer subsystems.
terrupt pending bits are denoted IxAPD through IxDPD
where “x” relates to the specific timer subsystem. There is
one system level interrupt request for each of the four timer
subsystems.
7
0
C1PRSC
==
Prescaler
Counter
TMOD1=11
Figure 107 illustrates the interrupt structure of the versatile
timer module.
I1AEN
I1BEN
T1RUN
I1CEN
I1DEN
15
0
I1APD
System
Restart
Count1[15:0]
Compare
PERCAP1[15:0]
15:0
I1BPD
I1CPD
I1DPD
Interrupt
Request 1
Compare
DTYCAP1[15:0]
I4AEN
te cap
rst
2
0
le ^C1EDG
TIO1
cap
rst
2
0
C2EDG
TIO2
I4BEN
I4CEN
I4DEN
I4APD
I4BPD
System
Interrupt
Request 4
DS092
I4CPD
Figure 106. VTU Dual 16-bit Capture Mode
26.1.4 Low Power Mode
In case a timer subsystem is not used, software can place it
o _{in a low-power mode. All clocks to a timer subsystem are}
stopped and the counter and prescaler contents are frozen
once low-power mode is entered. Software may continue to
write to the MODE, INTCTL, IOxCTL, and CLKxPS regis-
s _{ters. Write operations to the INTPND register are allowed;}
but if a timer subsystem is in low-power mode, its associat-
ed interrupt pending bits cannot be cleared. Software can-
not write to the COUNTx, PERCAPx, and DTYCAPx
b registers of a timer subsystem while it is in low-power mode.
All registers can be read at any time.
26.1.5 Interrupts
The VTU has a total of 16 interrupt sources, four for each of
O ^{the four timer subsystems. All interrupt sources have a}
I4DPD
DS093
Figure 107. VTU Interrupt Request Structure
Each of the timer pending bits - IxAPD through IxDPD - is
set by a specific hardware event depending on the mode of
operation, i.e., PWM or Capture mode. Table 73 outlines the
specific hardware events relative to the operation mode
which cause an interrupt pending bit to be set.
26.1.6 ISE Mode operation
The VTU supports breakpoint operation of the In-System-
Emulator (ISE). If FREEZE is asserted, all timer counter
clocks will be inhibited and the current value of the timer reg-
isters will be frozen; in capture mode, all further capture
events are disabled. Once FREEZE becomes inactive,
counting will resume from the previous value and the cap-
ture input events are re-enabled.
pending bit and an enable bit associated with them. All in-
Table 73 VTU Interrupt Sources
Pending Flag
IxAPD
IxBPD
IxCPD
IxDPD
Dual 8-bit PWM Mode
Low Byte Duty Cycle match
Low Byte Period match
High Byte Duty Cycle match
High Byte Period match
16-bit PWM Mode
Duty Cycle match
Period match
N/A
N/A
Capture Mode
Capture to PERCAPx
Capture to DTYCAPx
Counter Overflow
N/A
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